1. Field
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.
2. Information
In response to demands for faster, more efficient computer processing systems, attention has been directed to increasing throughput in many levels of such systems. For example, one such level may comprise a memory system, wherein a processor may generate read/write requests at a rate faster than the memory system can handle. Accordingly, techniques for dealing with such operating capability imbalances have led to development of multi-channel memory devices. Generally, a dual-channel memory device may incorporate two parallel channels to operate simultaneously to reduce latency involving memory read/write operations, for example. In particular, a memory controller may transmit and/or receive addressed read/write data to/from multiple memory arrays via two separate, parallel channels. Similarly, two separate, parallel host interfaces may be electronically connected to respective channels of a dual-channel memory device.